
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tbench/clk_reset_if/clk
   
add wave -noupdate -divider cpu_mst_axi4
add wave -noupdate -format Literal /tbench/cpu_mst_axi4/ARID
add wave -noupdate -format Literal /tbench/cpu_mst_axi4/ARQV
add wave -noupdate -format Logic /tbench/cpu_mst_axi4/ARVALID
add wave -noupdate -format Logic /tbench/cpu_mst_axi4/ARREADY
add wave -noupdate -format Literal /tbench/cpu_mst_axi4/RID
add wave -noupdate -format Logic /tbench/cpu_mst_axi4/RVALID
add wave -noupdate -format Logic /tbench/cpu_mst_axi4/RREADY
add wave -noupdate -format Logic /tbench/cpu_mst_axi4/RLAST

add wave -noupdate -divider dma_axi4_cpu_s
add wave -noupdate -format Literal /tbench/dma_axi4_cpu_s/ARID
add wave -noupdate -format Literal /tbench/dma_axi4_cpu_s/ARQV
add wave -noupdate -format Logic /tbench/dma_axi4_cpu_s/ARVALID
add wave -noupdate -format Logic /tbench/dma_axi4_cpu_s/ARREADY
add wave -noupdate -format Literal /tbench/dma_axi4_cpu_s/RID
add wave -noupdate -format Logic /tbench/dma_axi4_cpu_s/RVALID
add wave -noupdate -format Logic /tbench/dma_axi4_cpu_s/RREADY
add wave -noupdate -format Logic /tbench/dma_axi4_cpu_s/RLAST

add wave -noupdate -divider vgalcd_mst_axi4
add wave -noupdate -format Literal /tbench/vgalcd_mst_axi4/ARID
add wave -noupdate -format Literal /tbench/vgalcd_mst_axi4/ARQV
add wave -noupdate -format Logic /tbench/vgalcd_mst_axi4/ARVALID
add wave -noupdate -format Logic /tbench/vgalcd_mst_axi4/ARREADY
add wave -noupdate -format Literal /tbench/vgalcd_mst_axi4/RID
add wave -noupdate -format Logic /tbench/vgalcd_mst_axi4/RVALID
add wave -noupdate -format Logic /tbench/vgalcd_mst_axi4/RREADY
add wave -noupdate -format Logic /tbench/vgalcd_mst_axi4/RLAST

add wave -noupdate -divider chiplink_slv_axi4_tpv
add wave -noupdate -format Literal /tbench/chiplink_slv_axi4_tpv/ARID
add wave -noupdate -format Literal /tbench/chiplink_slv_axi4_tpv/ARQV
add wave -noupdate -format Literal /tbench/chiplink_slv_axi4_tpv/ARVALID
add wave -noupdate -format Logic /tbench/chiplink_slv_axi4_tpv/ARREADY
add wave -noupdate -format Literal /tbench/chiplink_slv_axi4_tpv/RID
add wave -noupdate -format Logic /tbench/chiplink_slv_axi4_tpv/RVALID
add wave -noupdate -format Logic /tbench/chiplink_slv_axi4_tpv/RREADY
add wave -noupdate -format Logic /tbench/chiplink_slv_axi4_tpv/RLAST

add wave -noupdate -divider sdram_slv_axi4
add wave -noupdate -format Literal /tbench/sdram_slv_axi4/ARID
add wave -noupdate -format Literal /tbench/sdram_slv_axi4/ARQV
add wave -noupdate -format Literal /tbench/sdram_slv_axi4/ARVALID
add wave -noupdate -format Logic /tbench/sdram_slv_axi4/ARREADY
add wave -noupdate -format Literal /tbench/sdram_slv_axi4/RID
add wave -noupdate -format Logic /tbench/sdram_slv_axi4/RVALID
add wave -noupdate -format Logic /tbench/sdram_slv_axi4/RREADY
add wave -noupdate -format Logic /tbench/sdram_slv_axi4/RLAST

add wave -noupdate -divider dma_axi4_cpu_m
add wave -noupdate -format Literal /tbench/dma_axi4_cpu_m/ARID
add wave -noupdate -format Literal /tbench/dma_axi4_cpu_m/ARQV
add wave -noupdate -format Literal /tbench/dma_axi4_cpu_m/ARVALID
add wave -noupdate -format Logic /tbench/dma_axi4_cpu_m/ARREADY
add wave -noupdate -format Literal /tbench/dma_axi4_cpu_m/RID
add wave -noupdate -format Logic /tbench/dma_axi4_cpu_m/RVALID
add wave -noupdate -format Logic /tbench/dma_axi4_cpu_m/RREADY
add wave -noupdate -format Logic /tbench/dma_axi4_cpu_m/RLAST

add wave -noupdate -divider uart_slv_apb4_tpv
add wave -noupdate -format Literal /tbench/uart_slv_apb4_tpv/ARID
add wave -noupdate -format Literal /tbench/uart_slv_apb4_tpv/ARQV
add wave -noupdate -format Literal /tbench/uart_slv_apb4_tpv/ARVALID
add wave -noupdate -format Logic /tbench/uart_slv_apb4_tpv/ARREADY
add wave -noupdate -format Literal /tbench/uart_slv_apb4_tpv/RID
add wave -noupdate -format Logic /tbench/uart_slv_apb4_tpv/RVALID
add wave -noupdate -format Logic /tbench/uart_slv_apb4_tpv/RREADY
add wave -noupdate -format Logic /tbench/uart_slv_apb4_tpv/RLAST

add wave -noupdate -divider spfs_slv_apb4_tpv
add wave -noupdate -format Literal /tbench/spfs_slv_apb4_tpv/ARID
add wave -noupdate -format Literal /tbench/spfs_slv_apb4_tpv/ARQV
add wave -noupdate -format Literal /tbench/spfs_slv_apb4_tpv/ARVALID
add wave -noupdate -format Logic /tbench/spfs_slv_apb4_tpv/ARREADY
add wave -noupdate -format Literal /tbench/spfs_slv_apb4_tpv/RID
add wave -noupdate -format Logic /tbench/spfs_slv_apb4_tpv/RVALID
add wave -noupdate -format Logic /tbench/spfs_slv_apb4_tpv/RREADY
add wave -noupdate -format Logic /tbench/spfs_slv_apb4_tpv/RLAST

add wave -noupdate -divider sram_slv_axi4
add wave -noupdate -format Literal /tbench/sram_slv_axi4/ARID
add wave -noupdate -format Literal /tbench/sram_slv_axi4/ARQV
add wave -noupdate -format Literal /tbench/sram_slv_axi4/ARVALID
add wave -noupdate -format Logic /tbench/sram_slv_axi4/ARREADY
add wave -noupdate -format Literal /tbench/sram_slv_axi4/RID
add wave -noupdate -format Logic /tbench/sram_slv_axi4/RVALID
add wave -noupdate -format Logic /tbench/sram_slv_axi4/RREADY
add wave -noupdate -format Logic /tbench/sram_slv_axi4/RLAST

add wave -noupdate -divider psram_slv_axi4
add wave -noupdate -format Literal /tbench/psram_slv_axi4/ARID
add wave -noupdate -format Literal /tbench/psram_slv_axi4/ARQV
add wave -noupdate -format Literal /tbench/psram_slv_axi4/ARVALID
add wave -noupdate -format Logic /tbench/psram_slv_axi4/ARREADY
add wave -noupdate -format Literal /tbench/psram_slv_axi4/RID
add wave -noupdate -format Logic /tbench/psram_slv_axi4/RVALID
add wave -noupdate -format Logic /tbench/psram_slv_axi4/RREADY
add wave -noupdate -format Logic /tbench/psram_slv_axi4/RLAST

add wave -noupdate -divider gpio_slv_apb4
add wave -noupdate -format Literal /tbench/gpio_slv_apb4/ARID
add wave -noupdate -format Literal /tbench/gpio_slv_apb4/ARQV
add wave -noupdate -format Literal /tbench/gpio_slv_apb4/ARVALID
add wave -noupdate -format Logic /tbench/gpio_slv_apb4/ARREADY
add wave -noupdate -format Literal /tbench/gpio_slv_apb4/RID
add wave -noupdate -format Logic /tbench/gpio_slv_apb4/RVALID
add wave -noupdate -format Logic /tbench/gpio_slv_apb4/RREADY
add wave -noupdate -format Logic /tbench/gpio_slv_apb4/RLAST

add wave -noupdate -divider uart_slv_apb4
add wave -noupdate -format Literal /tbench/uart_slv_apb4/ARID
add wave -noupdate -format Literal /tbench/uart_slv_apb4/ARQV
add wave -noupdate -format Literal /tbench/uart_slv_apb4/ARVALID
add wave -noupdate -format Logic /tbench/uart_slv_apb4/ARREADY
add wave -noupdate -format Literal /tbench/uart_slv_apb4/RID
add wave -noupdate -format Logic /tbench/uart_slv_apb4/RVALID
add wave -noupdate -format Logic /tbench/uart_slv_apb4/RREADY
add wave -noupdate -format Logic /tbench/uart_slv_apb4/RLAST

add wave -noupdate -divider pwm0_slv_apb4
add wave -noupdate -format Literal /tbench/pwm0_slv_apb4/ARID
add wave -noupdate -format Literal /tbench/pwm0_slv_apb4/ARQV
add wave -noupdate -format Literal /tbench/pwm0_slv_apb4/ARVALID
add wave -noupdate -format Logic /tbench/pwm0_slv_apb4/ARREADY
add wave -noupdate -format Literal /tbench/pwm0_slv_apb4/RID
add wave -noupdate -format Logic /tbench/pwm0_slv_apb4/RVALID
add wave -noupdate -format Logic /tbench/pwm0_slv_apb4/RREADY
add wave -noupdate -format Logic /tbench/pwm0_slv_apb4/RLAST

add wave -noupdate -divider i2c_slv_apb4
add wave -noupdate -format Literal /tbench/i2c_slv_apb4/ARID
add wave -noupdate -format Literal /tbench/i2c_slv_apb4/ARQV
add wave -noupdate -format Literal /tbench/i2c_slv_apb4/ARVALID
add wave -noupdate -format Logic /tbench/i2c_slv_apb4/ARREADY
add wave -noupdate -format Literal /tbench/i2c_slv_apb4/RID
add wave -noupdate -format Logic /tbench/i2c_slv_apb4/RVALID
add wave -noupdate -format Logic /tbench/i2c_slv_apb4/RREADY
add wave -noupdate -format Logic /tbench/i2c_slv_apb4/RLAST

add wave -noupdate -divider qspi_slv_apb4
add wave -noupdate -format Literal /tbench/qspi_slv_apb4/ARID
add wave -noupdate -format Literal /tbench/qspi_slv_apb4/ARQV
add wave -noupdate -format Literal /tbench/qspi_slv_apb4/ARVALID
add wave -noupdate -format Logic /tbench/qspi_slv_apb4/ARREADY
add wave -noupdate -format Literal /tbench/qspi_slv_apb4/RID
add wave -noupdate -format Logic /tbench/qspi_slv_apb4/RVALID
add wave -noupdate -format Logic /tbench/qspi_slv_apb4/RREADY
add wave -noupdate -format Logic /tbench/qspi_slv_apb4/RLAST

add wave -noupdate -divider archinfo_slv_apb4
add wave -noupdate -format Literal /tbench/archinfo_slv_apb4/ARID
add wave -noupdate -format Literal /tbench/archinfo_slv_apb4/ARQV
add wave -noupdate -format Literal /tbench/archinfo_slv_apb4/ARVALID
add wave -noupdate -format Logic /tbench/archinfo_slv_apb4/ARREADY
add wave -noupdate -format Literal /tbench/archinfo_slv_apb4/RID
add wave -noupdate -format Logic /tbench/archinfo_slv_apb4/RVALID
add wave -noupdate -format Logic /tbench/archinfo_slv_apb4/RREADY
add wave -noupdate -format Logic /tbench/archinfo_slv_apb4/RLAST

add wave -noupdate -divider crc_slv_apb4
add wave -noupdate -format Literal /tbench/crc_slv_apb4/ARID
add wave -noupdate -format Literal /tbench/crc_slv_apb4/ARQV
add wave -noupdate -format Literal /tbench/crc_slv_apb4/ARVALID
add wave -noupdate -format Logic /tbench/crc_slv_apb4/ARREADY
add wave -noupdate -format Literal /tbench/crc_slv_apb4/RID
add wave -noupdate -format Logic /tbench/crc_slv_apb4/RVALID
add wave -noupdate -format Logic /tbench/crc_slv_apb4/RREADY
add wave -noupdate -format Logic /tbench/crc_slv_apb4/RLAST

add wave -noupdate -divider spi0_slv_apb4
add wave -noupdate -format Literal /tbench/spi0_slv_apb4/ARID
add wave -noupdate -format Literal /tbench/spi0_slv_apb4/ARQV
add wave -noupdate -format Literal /tbench/spi0_slv_apb4/ARVALID
add wave -noupdate -format Logic /tbench/spi0_slv_apb4/ARREADY
add wave -noupdate -format Literal /tbench/spi0_slv_apb4/RID
add wave -noupdate -format Logic /tbench/spi0_slv_apb4/RVALID
add wave -noupdate -format Logic /tbench/spi0_slv_apb4/RREADY
add wave -noupdate -format Logic /tbench/spi0_slv_apb4/RLAST

add wave -noupdate -divider spi1_slv_apb4
add wave -noupdate -format Literal /tbench/spi1_slv_apb4/ARID
add wave -noupdate -format Literal /tbench/spi1_slv_apb4/ARQV
add wave -noupdate -format Literal /tbench/spi1_slv_apb4/ARVALID
add wave -noupdate -format Logic /tbench/spi1_slv_apb4/ARREADY
add wave -noupdate -format Literal /tbench/spi1_slv_apb4/RID
add wave -noupdate -format Logic /tbench/spi1_slv_apb4/RVALID
add wave -noupdate -format Logic /tbench/spi1_slv_apb4/RREADY
add wave -noupdate -format Logic /tbench/spi1_slv_apb4/RLAST

add wave -noupdate -divider clint_slv_apb4
add wave -noupdate -format Literal /tbench/clint_slv_apb4/ARID
add wave -noupdate -format Literal /tbench/clint_slv_apb4/ARQV
add wave -noupdate -format Literal /tbench/clint_slv_apb4/ARVALID
add wave -noupdate -format Logic /tbench/clint_slv_apb4/ARREADY
add wave -noupdate -format Literal /tbench/clint_slv_apb4/RID
add wave -noupdate -format Logic /tbench/clint_slv_apb4/RVALID
add wave -noupdate -format Logic /tbench/clint_slv_apb4/RREADY
add wave -noupdate -format Logic /tbench/clint_slv_apb4/RLAST

add wave -noupdate -divider plic_slv_apb4
add wave -noupdate -format Literal /tbench/plic_slv_apb4/ARID
add wave -noupdate -format Literal /tbench/plic_slv_apb4/ARQV
add wave -noupdate -format Literal /tbench/plic_slv_apb4/ARVALID
add wave -noupdate -format Logic /tbench/plic_slv_apb4/ARREADY
add wave -noupdate -format Literal /tbench/plic_slv_apb4/RID
add wave -noupdate -format Logic /tbench/plic_slv_apb4/RVALID
add wave -noupdate -format Logic /tbench/plic_slv_apb4/RREADY
add wave -noupdate -format Logic /tbench/plic_slv_apb4/RLAST

add wave -noupdate -divider rcu_slv_apb4
add wave -noupdate -format Literal /tbench/rcu_slv_apb4/ARID
add wave -noupdate -format Literal /tbench/rcu_slv_apb4/ARQV
add wave -noupdate -format Literal /tbench/rcu_slv_apb4/ARVALID
add wave -noupdate -format Logic /tbench/rcu_slv_apb4/ARREADY
add wave -noupdate -format Literal /tbench/rcu_slv_apb4/RID
add wave -noupdate -format Logic /tbench/rcu_slv_apb4/RVALID
add wave -noupdate -format Logic /tbench/rcu_slv_apb4/RREADY
add wave -noupdate -format Logic /tbench/rcu_slv_apb4/RLAST

add wave -noupdate -divider ps2_slv_apb4
add wave -noupdate -format Literal /tbench/ps2_slv_apb4/ARID
add wave -noupdate -format Literal /tbench/ps2_slv_apb4/ARQV
add wave -noupdate -format Literal /tbench/ps2_slv_apb4/ARVALID
add wave -noupdate -format Logic /tbench/ps2_slv_apb4/ARREADY
add wave -noupdate -format Literal /tbench/ps2_slv_apb4/RID
add wave -noupdate -format Logic /tbench/ps2_slv_apb4/RVALID
add wave -noupdate -format Logic /tbench/ps2_slv_apb4/RREADY
add wave -noupdate -format Logic /tbench/ps2_slv_apb4/RLAST

add wave -noupdate -divider rng_slv_apb4
add wave -noupdate -format Literal /tbench/rng_slv_apb4/ARID
add wave -noupdate -format Literal /tbench/rng_slv_apb4/ARQV
add wave -noupdate -format Literal /tbench/rng_slv_apb4/ARVALID
add wave -noupdate -format Logic /tbench/rng_slv_apb4/ARREADY
add wave -noupdate -format Literal /tbench/rng_slv_apb4/RID
add wave -noupdate -format Logic /tbench/rng_slv_apb4/RVALID
add wave -noupdate -format Logic /tbench/rng_slv_apb4/RREADY
add wave -noupdate -format Logic /tbench/rng_slv_apb4/RLAST

add wave -noupdate -divider tim0_slv_apb4
add wave -noupdate -format Literal /tbench/tim0_slv_apb4/ARID
add wave -noupdate -format Literal /tbench/tim0_slv_apb4/ARQV
add wave -noupdate -format Literal /tbench/tim0_slv_apb4/ARVALID
add wave -noupdate -format Logic /tbench/tim0_slv_apb4/ARREADY
add wave -noupdate -format Literal /tbench/tim0_slv_apb4/RID
add wave -noupdate -format Logic /tbench/tim0_slv_apb4/RVALID
add wave -noupdate -format Logic /tbench/tim0_slv_apb4/RREADY
add wave -noupdate -format Logic /tbench/tim0_slv_apb4/RLAST

add wave -noupdate -divider tim1_slv_apb4
add wave -noupdate -format Literal /tbench/tim1_slv_apb4/ARID
add wave -noupdate -format Literal /tbench/tim1_slv_apb4/ARQV
add wave -noupdate -format Literal /tbench/tim1_slv_apb4/ARVALID
add wave -noupdate -format Logic /tbench/tim1_slv_apb4/ARREADY
add wave -noupdate -format Literal /tbench/tim1_slv_apb4/RID
add wave -noupdate -format Logic /tbench/tim1_slv_apb4/RVALID
add wave -noupdate -format Logic /tbench/tim1_slv_apb4/RREADY
add wave -noupdate -format Logic /tbench/tim1_slv_apb4/RLAST

add wave -noupdate -divider tim2_slv_apb4
add wave -noupdate -format Literal /tbench/tim2_slv_apb4/ARID
add wave -noupdate -format Literal /tbench/tim2_slv_apb4/ARQV
add wave -noupdate -format Literal /tbench/tim2_slv_apb4/ARVALID
add wave -noupdate -format Logic /tbench/tim2_slv_apb4/ARREADY
add wave -noupdate -format Literal /tbench/tim2_slv_apb4/RID
add wave -noupdate -format Logic /tbench/tim2_slv_apb4/RVALID
add wave -noupdate -format Logic /tbench/tim2_slv_apb4/RREADY
add wave -noupdate -format Logic /tbench/tim2_slv_apb4/RLAST

add wave -noupdate -divider tim3_slv_apb4
add wave -noupdate -format Literal /tbench/tim3_slv_apb4/ARID
add wave -noupdate -format Literal /tbench/tim3_slv_apb4/ARQV
add wave -noupdate -format Literal /tbench/tim3_slv_apb4/ARVALID
add wave -noupdate -format Logic /tbench/tim3_slv_apb4/ARREADY
add wave -noupdate -format Literal /tbench/tim3_slv_apb4/RID
add wave -noupdate -format Logic /tbench/tim3_slv_apb4/RVALID
add wave -noupdate -format Logic /tbench/tim3_slv_apb4/RREADY
add wave -noupdate -format Logic /tbench/tim3_slv_apb4/RLAST

add wave -noupdate -divider psram_slv_apb4
add wave -noupdate -format Literal /tbench/psram_slv_apb4/ARID
add wave -noupdate -format Literal /tbench/psram_slv_apb4/ARQV
add wave -noupdate -format Literal /tbench/psram_slv_apb4/ARVALID
add wave -noupdate -format Logic /tbench/psram_slv_apb4/ARREADY
add wave -noupdate -format Literal /tbench/psram_slv_apb4/RID
add wave -noupdate -format Logic /tbench/psram_slv_apb4/RVALID
add wave -noupdate -format Logic /tbench/psram_slv_apb4/RREADY
add wave -noupdate -format Logic /tbench/psram_slv_apb4/RLAST

add wave -noupdate -divider rtc_slv_apb4
add wave -noupdate -format Literal /tbench/rtc_slv_apb4/ARID
add wave -noupdate -format Literal /tbench/rtc_slv_apb4/ARQV
add wave -noupdate -format Literal /tbench/rtc_slv_apb4/ARVALID
add wave -noupdate -format Logic /tbench/rtc_slv_apb4/ARREADY
add wave -noupdate -format Literal /tbench/rtc_slv_apb4/RID
add wave -noupdate -format Logic /tbench/rtc_slv_apb4/RVALID
add wave -noupdate -format Logic /tbench/rtc_slv_apb4/RREADY
add wave -noupdate -format Logic /tbench/rtc_slv_apb4/RLAST

add wave -noupdate -divider wdg_slv_apb4
add wave -noupdate -format Literal /tbench/wdg_slv_apb4/ARID
add wave -noupdate -format Literal /tbench/wdg_slv_apb4/ARQV
add wave -noupdate -format Literal /tbench/wdg_slv_apb4/ARVALID
add wave -noupdate -format Logic /tbench/wdg_slv_apb4/ARREADY
add wave -noupdate -format Literal /tbench/wdg_slv_apb4/RID
add wave -noupdate -format Logic /tbench/wdg_slv_apb4/RVALID
add wave -noupdate -format Logic /tbench/wdg_slv_apb4/RREADY
add wave -noupdate -format Logic /tbench/wdg_slv_apb4/RLAST

add wave -noupdate -divider pwm1_slv_apb4
add wave -noupdate -format Literal /tbench/pwm1_slv_apb4/ARID
add wave -noupdate -format Literal /tbench/pwm1_slv_apb4/ARQV
add wave -noupdate -format Literal /tbench/pwm1_slv_apb4/ARVALID
add wave -noupdate -format Logic /tbench/pwm1_slv_apb4/ARREADY
add wave -noupdate -format Literal /tbench/pwm1_slv_apb4/RID
add wave -noupdate -format Logic /tbench/pwm1_slv_apb4/RVALID
add wave -noupdate -format Logic /tbench/pwm1_slv_apb4/RREADY
add wave -noupdate -format Logic /tbench/pwm1_slv_apb4/RLAST

add wave -noupdate -divider pwm2_slv_apb4
add wave -noupdate -format Literal /tbench/pwm2_slv_apb4/ARID
add wave -noupdate -format Literal /tbench/pwm2_slv_apb4/ARQV
add wave -noupdate -format Literal /tbench/pwm2_slv_apb4/ARVALID
add wave -noupdate -format Logic /tbench/pwm2_slv_apb4/ARREADY
add wave -noupdate -format Literal /tbench/pwm2_slv_apb4/RID
add wave -noupdate -format Logic /tbench/pwm2_slv_apb4/RVALID
add wave -noupdate -format Logic /tbench/pwm2_slv_apb4/RREADY
add wave -noupdate -format Logic /tbench/pwm2_slv_apb4/RLAST

add wave -noupdate -divider vgalcd_slv_apb4
add wave -noupdate -format Literal /tbench/vgalcd_slv_apb4/ARID
add wave -noupdate -format Literal /tbench/vgalcd_slv_apb4/ARQV
add wave -noupdate -format Literal /tbench/vgalcd_slv_apb4/ARVALID
add wave -noupdate -format Logic /tbench/vgalcd_slv_apb4/ARREADY
add wave -noupdate -format Literal /tbench/vgalcd_slv_apb4/RID
add wave -noupdate -format Logic /tbench/vgalcd_slv_apb4/RVALID
add wave -noupdate -format Logic /tbench/vgalcd_slv_apb4/RREADY
add wave -noupdate -format Logic /tbench/vgalcd_slv_apb4/RLAST

add wave -noupdate -divider i2s_slv_apb4
add wave -noupdate -format Literal /tbench/i2s_slv_apb4/ARID
add wave -noupdate -format Literal /tbench/i2s_slv_apb4/ARQV
add wave -noupdate -format Literal /tbench/i2s_slv_apb4/ARVALID
add wave -noupdate -format Logic /tbench/i2s_slv_apb4/ARREADY
add wave -noupdate -format Literal /tbench/i2s_slv_apb4/RID
add wave -noupdate -format Logic /tbench/i2s_slv_apb4/RVALID
add wave -noupdate -format Logic /tbench/i2s_slv_apb4/RREADY
add wave -noupdate -format Logic /tbench/i2s_slv_apb4/RLAST

TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {0 ps} 0}
configure wave -namecolwidth 402
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {0 ps} {5000 ns}

